Isolation is an important and integral part of semiconductor device design and manufacturing. Isolation performs the important function of preventing the unwanted electrical coupling between adjacent parts of a transistor and between transistors. Sub-surface isolation in semiconductor devices are commonly achieved through p-n junctions and through insulating physical regions. Among the dielectric isolation processes, the most common are local oxidation of silicon (LOCOS)(sometimes referred to as recessed oxide (ROX) or Semi-recessed oxide (SROX)), shallow trench isolation (STI) and Deep Trench isolation (DTI). The resulting structure from LOCOS, ROX or SROX will be simply called recessed oxide isolation (ROI) in this text which is different from trench isolation.
FIG. 1A shows a prior art Field Effect Transistor (FET) device using an ROI isolation. In an ROI process, silicon substrate 10 is covered with a silicon nitride (SiN) mask layer and openings in the SiN mask layer correspond to the isolation pattern are defined (not shown). The exposed silicon surfaces are oxidized in a furnace, which results in SiO.sub.2 growth into and above the initial silicon surface, thereby forming a body of SiO.sub.2 20 above and below the surface of the substrate. The region covered by SiN is subsequently used to form a gate 50 and source/drain 60 regions. In ROI, the lateral and vertical dimensions of the oxide regions are determined by the oxidation mechanism, viz., diffusion and oxide growth. Usually the horizontal dimensions are large as compared to what is achievable in a trench type isolation. FIG. 1B shows the same structure shown in FIG. 1A, except the ROI has been replaced by trench isolation 30,40. In trench isolation, physical grooves are etched into a Si substrate and the grooves are filled with an insulating material such as silicon dioxide (SiO.sub.2). Trench isolation is an effective way to decouple lateral and vertical dimensions of the isolation. As shown in FIG. 1B, a shallow trench isolation 30, isolates adjacent device regions, source and drains 60 of adjacent FET devices within a well region 70, and a deep trench isolation 40 is used sometimes as a capacitor for storage. In forming a STI (or a DTI), the insulator fill process is selected as one that can fill a high aspect ratio trench satisfactorily without voids. This is a key consideration in selecting the lateral and vertical dimension of the trench isolation. This ability to independently shrink the horizontal isolation dimension, makes STI attractive for applications requiring high circuit density, an important objective in semiconductor design and manufacturing. As devices shrink, the depth of source and drain regions become shallow to increase the switching speed of the transistor. Correspondingly, the shallow trench regions also become shallow and narrow, which requires careful combination of unique etch, fill and clean processes.
A major concern in semiconductor processing, especially in CMOS devices, is mobile ionic impurities, such as sodium (Na), which can migrate to gate oxide regions and cause device performance to degrade. Further the migration of sodium ions to the bottom or sides of STI can lower field threshold and cause parasitic channelling. Mobile ions move rapidly, especially under voltage bias and cause gate instability. In semiconductor processing, photoresists, furnaces and wet chemicals are all known potential sources of Na impurities. A great deal of precaution is usually taken in process and materials to avoid introduction of the impurities. In addition, diffusion barrier layers and gettering layers are used to prevent any of the mobile ions from getting to the gate regions. A common practice is to deposit a layer of silicon nitride over gate regions as an impermeable layer to keep Na ions from reaching the gate region. Sometimes phosphosilicate glass (PSG) layers are used in contact with the gate region to actively getter any Na ions. The PSG forms a silicate with Na, thereby chemically ties up the Na ion. PSG layers and SiN are effective in preventing Na impurities introduced in silicon processing subsequent to gate/device formation and effective in protecting the device from Na ions introduced from subsequent processes. However, PSG layers are usually not effective if mobile ions are present under metal or nitride layers. This is the case with STI isolation, thus requiring a gettering layer built into the substrate.
Further, shallow trench isolation is formed prior to forming of the device regions. Current state of the art shallow trench isolation process can introduce mobile ion impurities from a multitude of processes such as groove patterning, etching, filling and planarizing steps. Therefore, there is a clear need to develop a process that will provide immunity to devices from Na ions introduced prior to device formation, a process that should be easily integrated with existing device processes and compatible with subsequent processes.